1. Field of the Invention
The present invention relates to a semiconductor package and a fabricating method therefor, and more particularly, to a chip size package (hereinafter abbreviated CSP) of a wafer level and a fabricating method therefor.
2. Discussion of Related Art
Recently, chip size package (CSP) technolgies have been introduced in the art of semiconductor packaging. The CSP technologies permit elecrical connections between a semiconductor chip and a circuit boad to be contained within the area below the periphery of the chip itself, such that the package can be nearly as small as the chip.
As one of the CSP technologies, a wafer level packaging technique in which the semiconductor chips can be packaged in a wafer state without being separated into individual chips is highlighted in the art.
Conventional packaging processes of the semiconductor hcip have been carried out after the wafer is divided into respective individual chips. Contrary to that, wafer level packaging processes are completed in the wafer state before the wafer is divided into the respective individual packages.
FIG. 1A to FIG. 1E show a process of fabricating a semiconductor package according to a related art.
The drawings illustrate a chip for a single package of a wafer. Left parts of the drawings show layouts of a package, while right parts show cross-sectional views of the package schematically.
Referring to FIG. 1A, chip pads 12 are formed on a semiconductor chip 11 on which predetermined patterns of circuit have been formed. The chip pads 12 connect the circuit of the semiconductor chip 11 to external circuits(not shown in the drawing).
Referring to FIG. 1B, a first insulating layer 13 covering an exposed surface of the semiconductor chip 11 is formed of an insulating substance for easing stress. One of polyimide and benzo-cyclobutane(BCB) may be used for the insulating substance for easing stress.
Then, contact holes exposing portions of the chip pads 12 are formed in the first insulating layer 13.
Referring to FIG. 1C, after a metal layer has been formed to cover the exposed portions of the chip pads 12 and the first insulating layer 13, a metal wiring layer 14 connected to the chip pads 12 is formed on the first insulating layer 13.
The metal wiring layer 14 usually consists of 2 to 3 layers for excellent electric conductivity between the semiconductor chip and the external circuits. Namely, after metal wiring layers of the same or different kind have been stacked, the metal wiring layer 14 is patterned by carrying out photolithography on the respective layers. Besides, an electroplated layer may be coated on the surface of the metal wiring layer 14 additionally to increase the thickness of the layer 14.
Referring to FIG. 1D, a second insulating layer 15 covering an exposed entire surface of the substrate is formed of an insulating substance to protect the metal wiring layer 14. Then, portions of the metal wiring layers 14 are exposed by forming contact holes through the second insulating layer 15.
Referring to FIG. 1E, solder balls 17 connected to the exposed portions of the metal wiring layers 14 are attached thereon. In this case, as the second insulating layer 15 is used as a solder mask layer by which solder balls are attached to the metal wiring layers 14 through flux screen printing, solder ball attachment, and reflowing.
In this case, in order to enhance the attachment between the solder ball 17 and the metal wiring layer 14, an under-bump metal layer 16 may be formed of a substance of which attachment capacity is very high therebetween.
Then, the fabrication of a semiconductor package is completed after following steps such as dicing, etc. have been carried out.
FIG. 2 shows a case of mounting a semiconductor package produced by the above-mentioned fabricating process on a printed circuit board(hereinafter abbreviated PCB).
Referring to FIG. 2, metal wiring layers 14 are connected to chip pads 12 on a semiconductor chip 11. A semiconductor package 10 of which solder balls 17 are connected to the metal wiring layers 14 is contacted with PCB pads 22 of a PCB substrate 21. That is, the semiconductor package 10 is mounted on the PCB substrate 21 while the solder balls 17 are connected to the PCB pads 22.
Unfortunately, reliability of a metal wire is very poor in the semiconductor package structure of the related art. While devices constructing the semiconductor chip are working, heat expansion between the PCB substrate and the semiconductor chip occurs due to resistance heat generated from the devices.
During this reaction, stress is concentrated on the solder balls connecting the PCB substrate and the semiconductor chip which produce the difference of heat expansion rate. Therefore, break-down of metal wire appears as the peripheral metal substances such as metal wiring layers, under-bump metal layers near the solder ball attached parts experience fatigue due to heat stress.
In the semiconductor package according to the related art, heat expansion rates of the chip pads of the semiconductor chip and the solder mask layer of the second insulating layer result in a great difference. Such difference in heat expansion rates between the chip pads and the solder mask layer causes the concentration of heat stress on the metal wiring layers lying therebetween, more particularly, on the portions of the metal wiring layers on the chip pads. Thereby, poor results such as breakdown and stripping of the metal wires on the chip pads occur.
Moreover, as the semiconductor package is fabricated through various steps of forming a first insulating layer for casing stress, forming multi-stacked metal wiring layers in use of sputtering apparatus, increasing the thickness of metal wiring layers, and etching respective metal layers in use of respective etchants, yield of the fabrication method of the semiconductor package is reduced due to the complicated steps of fabrication according to the related art.
Accordingly, the present invention is directed to a semiconductor package and a fabricating method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a semiconductor package and a fabricating method thereof which prevent the damages of metal wires in the related art from being generated by using both low-elastic stress-easing substances and polymer substances having electric conductivity.
Another object of the present invention is to provide a semiconductor package and a fabricating method thereof which simplify the fabrication steps by introducing the improved structure which is resulted from low-elastic stress-easing substances and polymer substances.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a semiconductor chip, a chip pad in a first area of the semiconductor chip, a stress-casing layer formed in a second area of the semiconductor chip, a conductive wire connecting the chip pad to the stress-easing layer, and an electrical conductor on the conductive wire over the stress-easing layer.
In another aspect, the present invention includes the steps of forming a chip pad on a first area of a semiconductor chip, forming a stress-easing layer on a second area of the semiconductor chip, forming a conductive wire connecting the chip pad to the stress-easing layer, and forming an electrical conductor on the conductive wire over the stress-easing layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.